PIC18F1230T-I/SO【PDF 76/318 页】IC PIC MCU FLASH 2KX16 18SOIC

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3871

72页 73页 74页 75页 [76页]77页 78页 79页 80页

PIC18F1230/1330

2009 Microchip Technology Inc.

DS39758D-page 167

15.4

EUSART Synchronous

Slave Mode

Synchronous Slave mode is entered by clearing bit,

CSRC (TXSTA<7>). This mode differs from the

Synchronous Master mode in that the shift clock is

supplied externally at the CK pin (instead of being

supplied internally in Master mode). This allows the

device to transfer or receive data while in any low-power

mode.

15.4.1

EUSART SYNCHRONOUS

SLAVE TRANSMISSION

The operation of the Synchronous Master and Slave

modes are identical, except in the case of the Sleep

mode.

If two words are written to the TXREG and then the

SLEEP

instruction is executed, the following will occur:

The first word will immediately transfer to the

TSR register and transmit.

The second word will remain in the TXREG

Flag bit, TXIF, will not be set.

When the first word has been shifted out of TSR,

the TXREG register will transfer the second

word to the TSR and flag bit, TXIF, will now be

set.

If enable bit, TXIE, is set, the interrupt will wake

the chip from Sleep. If the global interrupt is

enabled, the program will branch to the interrupt

vector.

To set up a Synchronous Slave Transmission:

Enable the synchronous slave serial port by

setting bits, SYNC and SPEN, and clearing bit,

CSRC.

Clear bits, CREN and SREN.

If interrupts are desired, set enable bit, TXIE.

If the signal from the CK pin is to be inverted, set

the TXCKP bit.

If 9-bit transmission is desired, set bit, TX9.

Enable the transmission by setting enable bit,

TXEN.

If 9-bit transmission is selected, the ninth bit

should be loaded in bit, TX9D.

Start transmission by loading data to the TXREG

If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

TABLE 15-9:

REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Values

on Page:

INTCON

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

PIR1

—

ADIF

RCIF

TXIF

CMP2IF

CMP1IF

CMP0IF

TMR1IF

PIE1

—

ADIE

RCIE

TXIE

CMP2IE

CMP1IE

CMP0IE

TMR1IE

IPR1

—

ADIP

RCIP

TXIP

CMP2IP

CMP1IP

CMP0IP

TMR1IP

RCSTA

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

TXREG

EUSART Transmit Register

TXSTA

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D

BAUDCON

ABDOVF

RCIDL

RXDTP

TXCKP

BRG16

—

WUE

ABDEN

SPBRGH

EUSART Baud Rate Generator Register High Byte

SPBRG

EUSART Baud Rate Generator Register Low Byte

Legend:

— = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式